AD8324ACPZ -3.3 V差分线驱动器IC

2022年1月13日 - 0评论

AD8324ACPZ线驱动程序

AD8324ACPZ PINOUT

AD8324是专为coaxial line driving。AD8324的功能最适合Docsis 2.0和Eurodocsis申请。The gain of the AD8324 is digitally controlled which has an 8-bit resolution over 59dB range, resulting in gain changes of 1 dB/LSB. The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 transformer. Distortion performance of –54 dBc is achieved with an output level up to 61 dBm at 65 MHz bandwidth. This device has a sleep mode function that reduces the quiescent current to 30 μA and a full power-down function that reduces the power-down current to 2.5 mA with a supply voltage of 3.3V.

AD8324ACPZ PINOUT配置

别针	引脚名称	描述
1、2、5、9、18、19	gnd	共同的外地参考
3	VIN+	非反转输入，DC偏向于大约VCC/2。必须与0.1μf电容器耦合
4	vin–	Inverting Input, DC-biased to approximately VCC/2. Must be ac-coupled with a 0.1 μF capacitor
6		Data Enable Low Input, This port controls the 8-bit parallel data latch and shift register. A Logic 0 to Logic 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A Logic 1 to Logic 0 transition inhibits the data latch (holds the previous and simultaneously enables the register for serial data load).
7	SDATA	串行数据输入，此数字输入允许首先将8位序列（增益）单词加载到内部寄存器中，并首先将最重要的位（MSB）加载到内部寄存器中。
8	clk	Clock Input, The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. Logic 0 to Logic 1 transition latches the data bit, and a Logic 1 to Logic 0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition.
10		低功率睡眠模式，在睡眠模式下，AD8324的供应电流降低至30μA。逻辑0为设备（高ZOUT状态）提供动力，而逻辑1为设备提供了动力。
11	NIC	没有内部连接，请勿连接到此PIN
12	BYP	内部旁路，该引脚必须在外部解耦（0.1μF电容器）。
13	vout-	Negative Output Signal, Must be biased to VCC.
14	VOUT+	正输出信号必须偏向VCC
15	坡道	外部坡道电容器（可选）
16	txen	传输启用，逻辑0禁用向前传输，逻辑1启用向前传输
17,20	VCC	普通的积极外部供应电压。
0	epad	接触垫,垫必须连接到公开a solid copper plane with low thermal resistance. This applies to the 20-lead LFCSP package only.

功能和规格

支持DOCSIS 2.0和EURODOCIS用于反向路径传输系统
在59 dB范围内以1 dB步长以1 dB的步骤进行编程
61 dbmv输出时低失真
输出噪声水平最小增益1.3 NV/√Hz
保持75Ω的输出阻抗，并在发射启用和
Upper bandwidth of 100 MHz (full gain range)
支持SPI®界面
Supply Voltage, VCC 3.63 V
输入电压1.5 V P-P
DATEN, SDATA, CLK, SLEEP, TXEN −0.5 V to +3.63 V
内部功率耗散776兆瓦
Operating Temperature Range −40°C to +85°C
可用的包装20量QSOP和20 LEAD LFCSP

笔记：完整的技术细节可以在AD8324ACPZ datasheet在此页面末尾给出。

等效的IC的AD8324ACPZ线驱动程序

DS8921，MT3608，DRV632，DRV135，AM26LS33

如何使用AD8324ACPZ线驱动程序IC

The AD8324 is primarily intended for use as the upstream power amplifier (PA) in Data-Over-Cable Service Interface Specification (DOCSIS) certified cable modems and CATV set-top boxes. The upstream signal is either a quadrature phase-shift keying (QPSK) or a quadrature amplitude modulation (QAM) signal generated by a digital signal processor (DSP), a dedicated QPSK/QAM modulator, or a digital-to-analog converter (DAC). In all cases, the signal must be low-pass filtered before it is applied to the PA in order to filter out-of-band noise and higher-order harmonics from the amplified signal.

由于电缆调制解调器和头端之间的距离不同，因此上游PA必须能够通过应用增益或衰减来改变输出功率。改变AD8324的输出功率的能力可确保电缆调制解调器的信号到达头顶时具有正确的水平。上游信号路径通常包括二元器和电缆拆分器。AD8324旨在克服与上游电缆路径中这些被动组件相关的损失。

AD8324 Application Circuit Diagram

The AD8324 is composed of three analog functions in the transmit enable mode. The input amplifier (preamp) can be used in a single-ended or differential configuration. If the input is used in the differential configuration, ensure that the input signals are 180° out of phase and of equal amplitude. A vernier is used in the input stage for controlling the fine 1 dB gain steps. This stage then drives a DAC that provides the bulk of the attenuation for the AD8324. The signals in the preamp and DAC blocks are differential to improve thepower supply rejection ratio（PSRR）和线性。从DAC馈入输出阶段的差分电流。输出阶段在所有功率模式下保持75Ω的差异输出阻抗。